1. Field of the Invention
The present invention is related to wafer characterization methods and measurements, and more particularly to a method, system and computer program product for isolating circuit or block level systematic differences from wafer measurement data and/or evaluation parameters computed therefrom.
2. Description of Related Art
Study of wafer-level measurement data variation, and/or evaluation parameters computed from measurement data, provides insight into several process mechanisms that cause significant differences in operation of circuits fabricated on a wafer. In particular systematic variations in etching and anneal processes across the wafer are typically independent of the systematic variations due to imaging processes, which cause variation on a particular basis. Characteristics of the wafer itself also may cause variation across the wafer. It is desirable to visualize and also to numerically characterize the wafer-level variation, so that processes and materials that cause such variation can be more uniformly controlled. Further, it is useful in debug of the design of circuits to eliminate such wafer-level variation as a source of a functionality or performance problem, for example when differences in performance are noted between multiple cores on a die. Once process variation is eliminated as a potential cause, then the design can be evaluated as to the underlying cause.
Within a given die, measurement data may be available from differing circuits that have differing features, e.g., circuits designed to measure different circuit parameters and/or functional circuits having different characteristics, but nonetheless exhibit variation due to the systematic wafer-level variation. Even if different circuits within a die are provided for measuring the same circuit parameter per-die and per-reticle systematic variations will typically be present. For the above reasons, a total collection of measurement data in general, and a visual display of the measurement data values or parameters computed from the measurement data values more specifically, typically yields a poor result in that all of the variation other than the wafer level variation contributes to visual and numerical “noise” that masks the wafer-level variation in other variation.
Therefore, existing techniques for visualizing and numerically mapping wafer-level variation typically either provide a display or map of one value per reticle, which may be aggregated and normalized, or may represent an individual circuit. Other visual displays and numerical maps present only the variation level per-reticle. Other systems that attempt to remove reticle level variation from wafer-level variation require generation of complex models that introduce error and are computationally and storage-allocation intensive.
Therefore, it would be desirable to provide an efficient method, system and computer program product for providing a display and/or numerical map of wafer-level variation that has been filtered to remove reticle/die level systematic variation and/or circuit level systematic differences and variation.